Trigate transistors and nanowire devices (i.e., transistors having bodies made from nanowires) typically have small geometries. For trigate transistors, the diffusion regions and the gates are typically quite thin.
FIG. 1 illustrates a properly-aligned prior art trigate transistor structure 5 comprised of two trigate transistors having respective gates 7 and 8 and a common diffusion region 10. Spacers 1 and 2 are adjacent to gate 7. Spacers 3 and 4 are adjacent to gate 8. Metallic contacts 21, 22, and 23 provide electrical contacts to diffusion region 10.
One of the problems associated with certain prior art trigate transistors and nanowire devices is that external electrical resistance (“Rext”) can sometimes be relatively high. High external electrical resistance can occur if metallic contacts are placed at some distance from the gate of a transistor with a thin diffusion body, such as a trigate transistor.
The placement of contacts 21, 22, and 23 shown in FIG. 1 is the goal in the prior art that is not always achieved, given the small geometries and lithography constraints. FIG. 2 shows trigate transistor structures 45 with a prior art contact misalignment problem. FIG. 3 shows transistor structure 45 in cross section. Contacts 31, 32, and 33 are misaligned with respect to respective gates 45 and 47 and respective spacers 52, 53, 54, and 55. A gap between a contact and a spacer (such as gap 42 between contact 32 and spacer 54) can result in higher Rext.
A device such as a static random-access memory (“SRAM”) uses numerous trigate transistors. Misalignment problems with contacts can lead to variations in Rext for the various trigate transistors, however, leading to less predicatability with respect to the design and performance of the overall integrated circuit. This can result in transistor mismatches.
One approach in the prior art for dealing with the misalignment high Rext problem has been the epitaxial growth of silicon at the source and drain prior to silicide formation in order to help to reduce the external resistance. One problem with that prior art approach, however, is that it is difficult to make a large enough area for a contact using epitaxial growth on a small silicon area—i.e., there is not much silicon to work with.
Another approach in the prior art for dealing with the misalignment high Rext problem has been to create a silicon diffusion jog to serve as a landing pad, as illustrated in FIG. 4. Diffusion jog 60 is an extension of diffusion layer 62 of transistor 64, which includes gate 66 and spacers 67 and 68. Diffusion jog 60 serves as a landing pad for contact 70 and thus acts as a contact pad.
The prior art landing pad approach can be problematic, however. Due to lithography constraints, the prior art landing pads typically must lie relatively far from the gate of the transistor. The landing pad requires more layout space. The thin silicon body of the diffusion layer and diffusion jog between the contact and the gate typically results in high external electrical resistance. Moreover, the landing pads can create undersirable jogs, sometimes causing problems for optical lithography, especially for sub-100 nanometer (“nm”) devices.
External electrical resistance problems can occur on devices beside trigate transistors. In principle, any transistor with a thin diffusion can have an Rext problem. The thin diffusion will result from lithography scaling, whether a trigate transistor is used or not. There can be Rext problems even on bulk devices on 65 nanometer nodes.
In the prior art, printing a rectangular contact in the diffusion direction sometimes can short the diffusion to the gate. Printing a rectangular contact in the direction perpendicular to the diffusion region can require more layout space.